Description Requirements • Diploma in Computer Science or Computer Engineering. • Physical presence at FORTH, Heraklion, Crete for the duration of the position. • Demonstrated experience with RTL design and simulations for FPGAs and high-level synthesis tools, such as Vitis HLS • Demonstrated familiarity with FPGA-based hardware implementation of accelerators • Experience in European Research Projects. • Fluent knowledge of the English language. • Names of at least three professional references. Desired qualifications Knowledge of and/or experience in and/or strong interest for: • RTL design and simulations with Vivado HLS tools • Alveo FPGA devices